Multilayer electrode for a ferroelectric capacitor

ABSTRACT

A ferroelectric or high dielectric constant capacitor having a multilayer lower electrode comprising at least two layers—a platinum layer and a platinum-rhodium layer—for use in a random access memory (RAM) cell. The platinum layer of the lower electrode adjoins the capacitor dielectric, which is a ferroelectric or high dielectric constant dielectric such as BST, PZT, SBT or tantalum pentoxide. The platinum-rhodium layer serves as an oxidation barrier and may also act as an adhesion layer for preventing separation of the lower electrode from the substrate, thereby improving capacitor performance. The multilayer electrode may have titanium and/or titanium nitride layers under the platinum-rhodium layer for certain applications. The capacitor has an upper electrode which may be a conventional electrode or which may have a multilayer structure similar to that of the lower electrode. Processes for manufacturing the multilayer lower electrode and the capacitor are also disclosed.

FIELD OF THE INVENTION

[0001] The present invention relates generally to a ferroelectric orhigh dielectric constant capacitor with a multilayer electrode, and inparticular to a ferroelectric or high dielectric constant capacitorwhich is used in a memory cell in a random access memory (RAM), and to aprocess for its formation.

BACKGROUND OF THE INVENTION

[0002] A dynamic random access memory (DRAM) cell typically comprises acharge storage capacitor (or cell capacitor) coupled to an access devicesuch as a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET).The MOSFET functions to apply or remove charge on the capacitor, thusaffecting a logical state defined by the stored charge. The amount ofcharge stored on the capacitor is determined by the capacitance C=εε_(o)A/d, where ε is the dielectric constant of the capacitor dielectric,ε_(o) is the vacuum permittivity, A is the electrode (or storage node)area, and d is the interelectrode spacing. The conditions of DRAMoperation such as operating voltage, leakage rate and refresh rate, willin general mandate that a certain minimum charge be stored by thecapacitor.

[0003] In the continuing trend to higher memory capacity, the packingdensity of storage cells must increase, yet each will maintain requiredcapacitance levels. This is a crucial demand of DRAM fabricationtechnologies if future generations of expanded memory array devices areto be successfully manufactured. Nevertheless, in the trend to highermemory capacity, the packing density of cell capacitors has increased atthe expense of available cell area. For example, the area allowed for asingle cell in a 64-Mbit DRAM is only about 1.4 μm². In such limitedareas, it is difficult to provide sufficient capacitance usingconventional stacked capacitor structures. Yet, design and operationalparameters determine the minimum charge required for reliable operationof the memory cell despite decreasing cell area. Several techniques havebeen developed to increase the total charge capacity of the cellcapacitor without significantly affecting the cell area. These includenew structures utilizing trench and stacked capacitors, electrodeshaving textured surface morphology and new capacitor dielectricmaterials having higher dielectric constants.

[0004] As DRAM density has increased (1 MEG and beyond) thin filmcapacitors, such as stacked capacitors, trenched capacitors, orcombinations thereof, have evolved in attempts to meet minimum spacerequirements. Many of these designs have become elaborate and difficultto fabricate consistently as well as efficiently. Furthermore, therecent generations of DRAMs (4 MEG and 16 MEG, for example) have pushedthin film capacitors technology to the limit of processing capability.Thus, greater attention has been given to the development of thin filmdielectric materials that possess a dielectric constant significantlygreater (>10x) than the conventional dielectrics used today, such assilicon oxides or nitrides.

[0005] Recently, a lot of attention has been paid to Barium StrontiumTitanate (BST), Barium Titanate (BT), Strontium Titanate (ST), LeadZirconate Titanate (PZT) and other high dielectric constant materials asa cell dielectric material of choice of DRAMs. These materials, inparticular BST, have a high dielectric constant (>300) and low leakagecurrents which makes them very attractive for high density memorydevices. However, there are some technical difficulties associated withthese materials. One problem with incorporating these materials intopresent day DRAM cell designs is their chemical reactivity with thepolycrystalline silicon (polysilicon or “poly”) that conventionallyforms the capacitor electrode or a buried electrode contact. Capacitorsmade by polysilicon-PZT/BST sandwiches undergo chemical and physicaldegradation with thermal processing. During chemical vapor deposition(CVD) of PZT/BST, oxygen in the ambient tends to oxidize the electrodematerial. The oxide is undesirable because it has a much lowerdielectric constant compared to PZT/BST, and adds in series to thecapacitance of the PZT/BST, thus drastically lowering the totalcapacitance of the capacitor. Therefore, even a thin native oxide layerpresent on the electrode results in a large degradation in capacitance.Furthermore, even when the electrode proper is made of a noble metal,such as Pt, oxygen will still tend to diffuse through it, contaminatingthe underlying polycrystalline silicon plug.

[0006] Ferroelectric memory devices have been proposed as alternativesto conventional memory devices. Ferroelectric memory devices utilize thespontaneous polarization properties of ferroelectric films to providedata storage elements which offer relatively fast read/write operationscompared with conventional storage elements. In addition, using acapacitor having a ferroelectric dielectric as a data storage device fora memory cell can reduce the power consumption of the memory cell andincrease operational speed as refresh operations typically are notrequired to maintain data in the capacitor. Moreover, such aferroelectric random access memory (FRAM) device may operate from asingle power supply voltage.

[0007] Generally, two types of FRAM cells are conventionally used: (1) atransistor employing a ferroelectric film as a gate insulation film, and(2) an access transistor connected to a cell capacitor employing aferroelectric film as a dielectric. Fabrication difficulties associatedwith the first type of cell include the potential formation of a siliconoxide film by reaction of silicon with oxygen atoms at the interfacebetween the silicon channel region of the transistor and theferroelectric gate insulation film. In addition, it may be difficult toform a high-quality ferroelectric film due to a lattice constantdifference or thermal expansion coefficient difference between thesilicon substrate and ferroelectric film.

[0008] For these reasons, conventional FRAM devices tend to employ thesecond structure described above, wherein a cell capacitor uses aferroelectric dielectric material as a dielectric. Typically, bariumstrontium titanate (BST) or lead zirconate titanate (PZT) are used forthe capacitor dielectric. According to a typical fabrication process,BST or PZT is deposited by a sol-gel process. The annealing temperatureof 500 to 650 degrees Celsius used during the heat treatment phase ofthe sol-gel process may deform a conventional aluminum electrode, oroxidize a tungsten electrode. Therefore, the lower electrode of aferroelectric capacitor is typically made of platinum because it has ahigh oxidation resistance and a high melting point.

[0009] Platinum is an excellent lower electrode material to use withferroelectric and high dielectric constant (HDC) dielectric materials.Platinum provides a low energy crystallization surface which catalyzesthe formation of perovskite crystals, it maintains its electricalproperties at the crystallization temperatures routinely used forsintering ferroelectric and HDC materials, and it is highly compatiblewith the ferroelectric properties of ferroelectric dielectric materials.

[0010] There are disadvantages to using platinum as an electrode,however, which are generally related to semiconductor processintegration. Platinum generally allows oxygen to diffuse through it andhence typically allows neighboring materials to oxidize. Platinum alsodoes not normally adhere well to traditional dielectrics such as silicondioxide, and the high degree of stress placed on the platinum-silicondioxide bond generated by the crystallization of the ferroelectric orHDC dielectric material peels the platinum off the substrate duringprocessing. It may also rapidly form a silicide at low temperatures, andalso may form hillocks which degrade leakage current properties or shortout the capacitor. In addition, alpha-particle creation by theradioactive isotope of platinum (Pt-190), which is typically present asa small percentage of the total platinum atoms in a sample, may bedetrimental to the electrical functioning of the capacitor.

[0011] There is needed, therefore an improved lower electrode for aferroelectric or high dielectric constant capacitor having theadvantages of a platinum electrode while avoiding problems of oxidationand separation from the substrate. A simple method of fabricating animproved lower electrode is also needed.

BRIEF SUMMARY OF THE INVENTION

[0012] The present invention provides a ferroelectric or high dielectricconstant capacitor with a multilayer lower electrode for use in a RAM orFRAM memory cell. The multilayer lower electrode has at least twolayers - a platinum layer adjacent the dielectric, and aplatinum-rhodium layer beneath the platinum layer. The platinum-rhodiumlayer serves as an oxidation barrier and may also act as an adhesionlayer for preventing separation of the lower electrode from thesubstrate, thereby improving capacitor performance. Titanium and/ortitanium nitride layers may be used under the platinum-rhodium layer ifdesired. A ferroelectric or HDC dielectric material is used as thecapacitor dielectric, and the upper electrode may take the form of aconventional upper electrode, or may have the same multilayer structureas the lower electrode. Also provided are processes for manufacturingthe multilayer lower electrode.

[0013] Additional advantages and features of the present invention willbe apparent from the following detailed description and drawings whichillustrate preferred embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 is a cross-sectional view of the ferroelectric capacitor ofa preferred embodiment of the present invention.

[0015]FIG. 2 is a cross-sectional view of the ferroelectric capacitor ofa second embodiment of the present invention.

[0016]FIG. 3 is a cross-sectional view of the ferroelectric capacitor ofa third embodiment of the present invention.

[0017]FIG. 4 is a cross-sectional view of a semiconductor substratehaving transistors and an insulating layer formed thereon.

[0018]FIG. 5 shows the substrate of FIG. 4 undergoing the process of apreferred embodiment of the present invention.

[0019]FIG. 6 shows the substrate of FIG. 5 at a processing stepsubsequent to that shown in FIG. 5.

[0020]FIG. 7 shows the substrate of FIG. 5 at a processing stepsubsequent to that shown in FIG. 6.

[0021]FIG. 8 shows the substrate of FIG. 5 at a processing stepsubsequent to that shown in FIG. 7.

[0022]FIG. 9 shows the substrate of FIG. 4 undergoing the process of asecond embodiment of the present invention.

[0023]FIG. 10 shows the substrate of FIG. 9 at a processing stepsubsequent to that shown in FIG. 9.

[0024]FIG. 11 shows the substrate of FIG. 9 at a processing stepsubsequent to that shown in FIG. 10.

[0025]FIG. 12 shows the substrate of FIG. 9 at a processing stepsubsequent to that shown in FIG. 11.

[0026]FIG. 13 shows the substrate of FIG. 9 at a processing stepsubsequent to that shown in FIG. 12.

[0027]FIG. 14 shows the substrate of FIG. 9 at a processing stepsubsequent to that shown in FIG. 13.

[0028]FIG. 15 shows the substrate of FIG. 4 undergoing the process of athird embodiment of the present invention.

[0029]FIG. 16 shows the substrate of FIG. 15 at a processing stepsubsequent to that shown in FIG. 15.

[0030]FIG. 17 shows the substrate of FIG. 15 at a processing stepsubsequent to that shown in FIG. 16.

[0031]FIG. 18 shows the substrate of FIG. 15 at a processing stepsubsequent to that shown in FIG. 17.

[0032]FIG. 19 shows the substrate of FIG. 15 at a processing stepsubsequent to that shown in FIG. 18.

[0033]FIG. 20 shows the substrate of FIG. 15 at a processing stepsubsequent to that shown in FIG. 19.

[0034]FIG. 21 shows the substrate of FIG. 15 at a processing stepsubsequent to that shown in FIG. 20.

[0035]FIG. 22 is an illustration of a computer system having aferroelectric capacitor according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0036] In the following detailed description, reference is made to theaccompanying drawings which form a part hereof, and in which is shown byway of illustration specific embodiments in which the invention may bepracticed. These embodiments are described in sufficient detail toenable those skilled in the art to practice the invention, and it is tobe understood that other embodiments may be utilized, and thatstructural, logical and electrical changes may be made without departingfrom the spirit and scope of the present invention.

[0037] The terms “wafer” and “substrate” are to be understood asincluding silicon-on-insulator (SOI) or silicon-on-sapphire (SOS)technology, doped and undoped semiconductors, epitaxial layers ofsilicon supported by a base semiconductor foundation, and othersemiconductor structures. Furthermore, when reference is made to a“wafer” or “substrate” in the following description, previous processsteps may have been utilized to form regions or junctions in the basesemiconductor structure or foundation. In addition, the semiconductorneed not be silicon-based, but could be based on silicon-germanium,germanium, or gallium arsenide.

[0038] The term “high dielectric constant dielectric material” or “HDCdielectric material” as used herein refers to dielectric materialshaving high dielectric constants (ε=˜20 or higher), and including, butnot limited to barium strontium titanate (BST or Ba_(x)Sr_((1-x))TiO₃),lead zirconate titanate (PZT or PbZr_((1-x))Ti_(x)O₃), lead lanthanumzirconate titanate (PLZT), lead scandium tantalate (PST), strontiumbismuth tantalate (SBT or SrBi₂Ta₂O₉), barium bismuth tantalate (BBT orBaBi₂Ta₂O₉), barium titanate (BT or BaTiO₃), strontium titanate (ST orSrTiO₃), tantalum pentoxide (Ta₂O₅), and other metallic oxides havingperovskite or ilmenite crystal structures and high dielectric constants(ε=˜20 or higher). The following detailed description is, therefore, notto be taken in a limiting sense, and the scope of the present inventionis defined by the appended claims.

[0039] Referring now to the drawings, where like elements are designatedby like reference numerals, an embodiment of the capacitor 40 of thepresent invention is shown in FIG. 1. The capacitor 40 is formed on asilicon substrate 50 having word line 52 and active areas 54, 56 forminga transistor 58 thereon. An oxide layer 60 of a material such as silicondioxide is formed over the transistor 58, and a conductive plug 62 ofdoped polysilicon, tungsten, or other suitable material extends throughthe oxide layer 60 to form a contact to active area 54. Protective layer64 is formed over the oxide layer 60, and is of a material such asborophosphosilicate glass (BPSG), borosilicate glass (BSG),phosphosilicate glass (PSG), or silicon dioxide. The capacitor 40 isformed in the protective layer 64 over the conductive plug 62.

[0040] The capacitor 40 comprises an upper electrode 70, a dielectriclayer 72, and a lower electrode having multiple layers. The upperelectrode 70 may be comprised of any suitable material such as titaniumnitride, tungsten, tungsten nitride, platinum, palladium, tantalum,tantalum nitride, aluminum, molybdenum, polysilicon, or othersemiconductor conducting materials, or may have a structure identical tothat of an embodiment of the lower electrode of this invention, as isfurther described below. The dielectric layer 72 may be any HDCdielectric material described above, but preferably is BST, PZT, SBT, ortantalum pentoxide, and has a thickness of less than about 5000Angstroms, preferably less than about 500 Angstroms.

[0041] As shown in FIGS. 1 through 3, the lower electrode comprises atleast two layers—a platinum layer 74 and a platinum-rhodium layer76—formed on the protective layer 64. FIG. 2 depicts a capacitor 240 ofa second embodiment, in which the lower electrode has an additionaltitanium layer 78 formed between the platinum-rhodium layer 76 and theprotective layer 64, and FIG. 3 shows a capacitor 340 of a thirdembodiment, in which an additional titanium nitride layer 80 is presentbetween the titanium layer 78 and the protective layer 64. Thecapacitors 240, 340 of the second and third embodiments may also have asilicide layer 82 formed between the lower electrode and the protectivelayer 64 as a result of the fabrication process, as shown in FIGS. 2 and3.

[0042] Referring now to FIGS. 1 through 3, the platinum layer 74 of thelower electrode is typically about 50 to about 300 Angstroms thick,preferably about 50 to about 150 Angstroms, and the platinum-rhodiumlayer 76 is typically from about 100 to about 800 Angstroms thick,preferably about 150 to about 300 Angstroms. The platinum-rhodium layer76 is comprised of an alloy having a composition of approximately 3 toapproximately 40 percent rhodium and approximately 97 to approximately60 percent platinum by weight. The titanium layer 78 of the lowerelectrode, if it is present, is about 60 to about 200 Angstroms thick,preferably about 60 to about 100 Angstroms, and the titanium nitridelayer 80 is about 100 to about 200 Angstroms thick, preferably about 100to about 150 Angstroms.

[0043] The capacitor 40 is manufactured through a process that beginswith the structure illustrated by FIG. 4. The process begins subsequentto the formation of the word line 52, active areas 54, 56, oxide layer60, conductive plug 62 and protective layer 64. A resist 90 (not shown)is applied, and photolithographic techniques are used to define an areato be etched-out. An etching process such as wet etching using an acidsuch as nitric and/or hydrofluoric acid, or dry etching methods such asplasma etching or reactive ion etching (RIE) is used to etch through theprotective layer 64 to expose the conductive plug 62 and form a trench92, as shown in FIG. 4. The photoresist is then stripped.

[0044] The capacitor 40 of the preferred embodiment is then manufacturedthrough a process described as following, and illustrated by FIGS. 5through 8. As shown in FIG. 5, the first step in the process is to formthe platinum-rhodium layer 76 on the surface of the protective layer 64and in the trench 92. This layer may be formed by means such as chemicalvapor deposition (CVD), physical vapor deposition (PVD), sputtering,evaporation, or other suitable means, and is formed to a thickness ofabout 100 to about 800 Angstroms, preferably about 150 to about 300Angstroms. The platinum-rhodium layer 76 is an alloy comprisingapproximately 3 to approximately 40 percent rhodium and approximately 97to approximately 60 percent platinum by weight.

[0045]FIG. 6 depicts the next step, in which the platinum layer 74 isformed on the surface of the platinum-rhodium layer 76 by suitable meanssuch as CVD, PVD, sputtering, or evaporation. This layer has a thicknessof about 50 to about 300 Angstroms, preferably about 50 to about 150Angstroms. A preferred method of forming the platinum-rhodium andplatinum layers 76, 74 is in-situ CVD. In this method, the substrate 50is placed in a CVD reactor, and platinum and rhodium precursors areintroduced into the reactor chamber to form the platinum-rhodium layer76. When the platinum-rhodium layer 76 has been formed to the desiredthickness, the flow of rhodium precursor is shut off so that theplatinum layer 74 may then be formed. Another preferred method offorming these layers uses a CVD reactor with two ampoules. The firstampoule is charged with a mixture of platinum and rhodium precursors,and the second ampoule is charged only with platinum precursors. Theplatinum-rhodium layer 76 is formed using the first ampoule, and thenthe platinum layer 74 is formed using the second ampoule. This methodachieves better process stability than other known methods.

[0046] The dielectric layer 72 is then formed over the platinum layer74, as illustrated by FIG. 7. The dielectric layer 72, which may be alayer of any of the HDC dielectric materials described above, is thenformed. The HDC dielectric material, which is preferably BST, PZT, SBT,or tantalum pentoxide, may be formed by any suitable process such asspinning, sputtering, CVD, ion beam sputtering, laser beam deposition,molecular beam epitaxy (MBE), evaporation, or a sol-gel process.Typically a sol-gel process is used. In this process, a solution or solcontaining the desired oxide or non-oxide precursor is formulated andapplied to the surface of the platinum layer 74 by spinning, dipping ordraining. The resultant dielectric layer 72 is then dried at a lowtemperature, e.g., 100 degrees Celsius, and then treated by exposing itto high temperatures (300 to 1100 degrees Celsius) for a period of timesufficient to drive water and solvent out of the layer and to form ahard dielectric layer 72.

[0047] Referring now to FIG. 8, the upper electrode 70 is formed on thedielectric layer. The upper electrode 70 may be a single layer ofsuitable conductive material such as titanium nitride, tungsten nitride,platinum, or polysilicon, or may have a multilayer structure identicalto that of the lower electrode, with a platinum layer and aplatinum-rhodium layer. CVD, PVD, sputtering, evaporation, or othersuitable means may be used to form the upper electrode 70, and the meanschosen will vary depending on the desired structure and materials, as isknown in the art. The capacitor 40 now appears as shown in FIG. 8.Further steps to create a functional memory cell containing thecapacitor 40 may now be carried out, such as the formation and etchingof insulating layers, e.g., BPSG, PSG, BSG, silicon dioxide or the like,to form conduits for electrical contacts (not shown), and for additionalinsulating, passivating, and wiring interconnect layers.

[0048] A second embodiment of the capacitor 240 may be manufacturedstarting with the structure of FIG. 4 by a process depicted in FIGS. 9through 14, and as described below. Referring to FIG. 9, a titaniumlayer 78 is formed on the surface of the protective layer 64 and in thetrench 92 by means such as CVD, PVD, sputtering or evaporation. Thetitanium layer is formed to a thickness of about 60 to about 200Angstroms, preferably about 60 to about 100 Angstroms. Next, as shown inFIG. 10, the platinum-rhodium layer 76 is formed by a suitable processsuch as CVD, as explained with reference to FIG. 5 above.

[0049]FIG. 11 depicts the next step in which the platinum layer 74 isformed on the surface of the platinum-rhodium layer 76. The dielectriclayer 72 is then formed on the platinum-rhodium layer 76 by a sol-gelprocess, as shown in FIG. 12. During the heat treatment phase of thesol-gel process, a silicide layer 82 may be formed by an interactionbetween the titanium layer 78 and silicon of the oxide layer 60 and/orthe conductive plug 62, depending on the material of the conductive plug62, as shown in FIG. 13. Formation of the silicide layer 82 results in alower contact resistance between the titanium layer 78 and theconductive plug 62.

[0050] Referring now to FIG. 14, the upper electrode 70 is formed on thedielectric layer, and may be a single layer of suitable conductivematerial, or a multilayer structure identical to that of the lowerelectrode, as is described above with reference to FIG. 8. The capacitor240 now appears as shown in FIG. 14. Further steps to create afunctional memory cell containing the capacitor may now be carried out,such as the formation and etching of insulating layers, e.g., BPSG, PSG,BSG, silicon dioxide or the like, to form conduits for electricalcontacts (not shown), and for additional insulating, passivating, andwiring interconnect layers.

[0051] A third embodiment of the capacitor 340 may be manufacturedstarting with the structure of FIG. 4 by a process depicted in FIGS. 15through 21, and as described below. Referring to FIG. 15, a titaniumnitride layer 80 is formed on the surface of the protective layer 64 andin the trench 92 by means such as CVD, PVD, sputtering or evaporation.The titanium nitride layer 80 is formed to a thickness of about 100 toabout 200 Angstroms thick, preferably about 100 to about 150 Angstroms.Next, as shown in FIGS. 16 and 17, the titanium layer 78 andplatinum-rhodium layer 76 are formed by suitable processes such as CVD,as explained with reference to FIGS. 9 and 10 above.

[0052]FIG. 18 depicts the next step in which the platinum layer 74 isformed on the surface of the platinum-rhodium layer 76. The dielectriclayer 72 is then formed on the platinum-rhodium layer 76 by a sol-gelprocess, as shown in FIG. 19. During the heat treatment phase of thesol-gel process, a silicide layer 82 may be formed by an interactionbetween the titanium nitride layer 80 and silicon of the oxide layer 60and/or the conductive plug 62, depending on the material of theconductive plug 62, as shown in FIG. 20. Formation of the silicide layer82 results in a lower contact resistance between the titanium nitridelayer 80 and the conductive plug 62.

[0053] Referring now to FIG. 21, the upper electrode 70 is formed on thedielectric layer, and may be a single layer of suitable conductivematerial, or a multilayer structure identical to that of the lowerelectrode, as is described above with reference to FIG. 8. The capacitor340 now appears as shown in FIG. 21. Further steps to create afunctional memory cell containing the capacitor may now be carried out,such as the formation and etching of insulating layers, e.g., BPSG, PSG,BSG, silicon dioxide or the like, to form conduits for electricalcontacts (not shown), and for additional insulating, passivating, andwiring interconnect layers.

[0054] As can be seen by the embodiments described herein, the presentinvention encompasses HDC and ferroelectric capacitors having multilayerelectrode stacks, and processes of forming the same. As may be readilyappreciated by persons skilled in the art, the platinum andplatinum-rhodium layers of the lower electrode serve as oxidationbarriers and exhibit improved adhesion to the substrate, therebyproviding improved stability and performance of the capacitor.

[0055] A typical processor based system which includes a memorycontaining capacitors according to the present invention is illustratedgenerally at 400 in FIG. 22. A processor based system is exemplary of asystem having digital circuits which could include ferroelectric or HDCcapacitor devices. A processor system, such as a computer system, forexample generally comprises a central processing unit (CPU) 444, e.g., amicroprocessor, that communicates with an input/output (I/O) device 446over a bus 452. The memory 448 also communicates with the system overbus 452. In the case of a computer system the processor system mayinclude peripheral devices such as a floppy disk drive 454 and a compactdisk (CD) ROM drive 456 which also communicate with CPU 444 over the bus452. Memory 448 is preferably constructed as an integrated circuit whichincludes capacitors having multilayer electrodes, as previouslydescribed with respect to FIGS. 1 to 21. The memory 448 may be combinedwith a processor, such as a CPU, digital signal processor ormicroprocessor, with or without memory storage, in a single integratedcircuit.

[0056] It should again be noted that although the invention has beendescribed with specific reference to memory circuits and ferroelectricand HDC capacitors, the invention has broader applicability and may beused in any integrated circuit requiring capacitors. Similarly, theprocess described above is but one method of many that could be used.Accordingly, the above description and drawings are only illustrative ofpreferred embodiments which achieve the objects, features and advantagesof the present invention. It is not intended that the present inventionbe limited to the illustrated embodiments. Any modification of thepresent invention which comes within the spirit and scope of thefollowing claims should be considered part of the present invention.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A ferroelectric or high dielectric constantcapacitor electrode, comprising: an electrode having a platinum-rhodiumlayer and a platinum layer on top of the platinum-rhodium layer.
 2. Thecapacitor of claim 1 , wherein the platinum-rhodium layer comprises analloy comprising approximately 3 to approximately 40 percent rhodium. 3.The capacitor of claim 2 , wherein the alloy further comprisesapproximately 60 to approximately 97 percent platinum.
 4. The capacitorof claim 1 , wherein the platinum-rhodium layer has a thickness withinthe range of about 100 to about 800 Angstroms.
 5. The capacitor of claim1 , wherein the platinum-rhodium layer has a thickness within the rangeof about 150 to about 300 Angstroms.
 6. The capacitor of claim 1 ,wherein the platinum layer has a thickness within the range of about 50to about 300 Angstroms.
 7. The capacitor of claim 1 , wherein theplatinum layer has a thickness within the range of about 50 to about 150Angstroms.
 8. The capacitor of claim 1 , further comprising a titaniumlayer beneath the platinum-rhodium layer.
 9. The capacitor of claim 8 ,wherein the titanium layer has a thickness within the range of about 60to about 200 Angstroms.
 10. The capacitor of claim 8 , wherein thetitanium layer has a thickness within the range of about 60 to about 100Angstroms.
 11. The capacitor of claim 8 , further comprising a titaniumnitride layer beneath the titanium layer.
 12. The capacitor of claim 11, wherein the titanium nitride layer has a thickness within the range ofabout 100 to about 200 Angstroms.
 13. The capacitor of claim 11 ,wherein the titanium nitride layer has a thickness within the range ofabout 100 to about 150 Angstroms.
 14. A capacitor, comprising: a lowerelectrode having a platinum-rhodium layer and a platinum layer on top ofthe platinum-rhodium layer; an upper electrode; and a dielectric layerof a ferroelectric or high dielectric constant dielectric materialformed between said lower and upper electrodes, wherein said dielectriclayer is in contact with the platinum layer of said lower electrode. 15.The capacitor of claim 14 , wherein the platinum-rhodium layer comprisesan alloy comprising approximately 60 to approximately 97 percentplatinum.
 16. The capacitor of claim 15 , wherein the alloy furthercomprises approximately 3 to approximately 40 percent rhodium.
 17. Thecapacitor of claim 14 , wherein the platinum-rhodium layer has athickness within the range of about 100 to about 800 Angstroms.
 18. Thecapacitor of claim 14 , wherein the platinum-rhodium layer has athickness within the range of about 150 to about 300 Angstroms.
 19. Thecapacitor of claim 14 , wherein the platinum layer has a thicknesswithin the range of about 50 to about 300 Angstroms.
 20. The capacitorof claim 14 , wherein the platinum layer has a thickness within therange of about 50 to about 150 Angstroms.
 21. The capacitor of claim 14, further comprising a titanium layer beneath the platinum-rhodiumlayer.
 22. The capacitor of claim 21 , wherein the titanium layer has athickness within the range of about 60 to about 200 Angstroms.
 23. Thecapacitor of claim 21 , wherein the titanium layer has a thicknesswithin the range of about 60 to about 100 Angstroms.
 24. The capacitorof claim 21 , further comprising a titanium nitride layer beneath thetitanium layer.
 25. The capacitor of claim 24 , wherein the titaniumnitride layer has a thickness within the range of about 100 to about 200Angstroms.
 26. The capacitor of claim 24 , wherein the titanium nitridelayer has a thickness within the range of about 100 to about 150Angstroms.
 27. The capacitor of claim 14 , wherein the upper electrodehas a conductive layer.
 28. The capacitor of claim 27 , wherein theconductive layer is a layer of material selected from the groupconsisting of titanium nitride, tungsten nitride, platinum, andpolysilicon.
 29. The capacitor of claim 14 , wherein the upper electrodehas a platinum layer and a platinum-rhodium layer on top of the platinumlayer.
 30. The capacitor of claim 14 , wherein the dielectric layer hasa thickness of less than about 5000 Angstroms.
 31. The capacitor ofclaim 14 , wherein the dielectric layer has a thickness of less thanabout 500 Angstroms.
 32. The capacitor of claim 14 , wherein thedielectric material is a metallic oxide having a perovskite or ilmenitecrystal structure and a dielectric constant of approximately 20 orhigher.
 33. The capacitor of claim 14 , wherein the dielectric materialis selected from the group consisting of PLZT, PST, BBT, BT, and ST. 34.The capacitor of claim 14 , wherein the dielectric material is BST. 35.The capacitor of claim 14 , wherein the dielectric material is PZT. 36.The capacitor of claim 14 , wherein the dielectric material is SBT. 37.The capacitor of claim 14 , wherein the dielectric material is tantalumpentoxide.
 38. A capacitor, comprising: a lower electrode having atitanium layer, an alloy layer on top of the titanium layer, wherein thealloy layer comprises approximately 60 to approximately 97 percentplatinum and approximately 3 to approximately 40 percent rhodium, and aplatinum layer on top of the alloy layer; an upper electrode; and adielectric layer of a ferroelectric or high dielectric constantdielectric material formed between said lower and upper electrodes,wherein said dielectric layer is in contact with the platinum layer ofsaid lower electrode.
 39. The capacitor of claim 38 , wherein thetitanium layer has a thickness within the range of about 60 to about 200Angstroms.
 40. The capacitor of claim 38 , wherein the titanium layerhas a thickness within the range of about 60 to about 100 Angstroms. 41.The capacitor of claim 38 , wherein the alloy layer has a thicknesswithin the range of about 100 to about 800 Angstroms.
 42. The capacitorof claim 38 , wherein the alloy layer has a thickness within the rangeof about 150 to about 300 Angstroms.
 43. The capacitor of claim 38 ,wherein the platinum layer has a thickness within the range of about 50to about 300 Angstroms.
 44. The capacitor of claim 38 , wherein theplatinum layer has a thickness within the range of about 50 to about 150Angstroms.
 45. The capacitor of claim 38 , further comprising a titaniumnitride layer beneath the titanium layer.
 46. The capacitor of claim 45, wherein the titanium nitride layer has a thickness within the range ofabout 100 to about 200 Angstroms.
 47. The capacitor of claim 45 ,wherein the titanium nitride layer has a thickness within the range ofabout 100 to about 150 Angstroms.
 48. The capacitor of claim 38 ,wherein the upper electrode has a conductive layer.
 49. The capacitor ofclaim 48 , wherein the conductive layer is a layer of material selectedfrom the group consisting of titanium nitride, tungsten nitride,platinum, and polysilicon.
 50. The capacitor of claim 38 , wherein theupper electrode has a platinum layer and a platinum-rhodium layer on topof the platinum layer.
 51. The capacitor of claim 38 , wherein thedielectric layer has a thickness of less than about 5000 Angstroms. 52.The capacitor of claim 38 , wherein the dielectric layer has a thicknessof less than about 500 Angstroms.
 53. The capacitor of claim 38 ,wherein the dielectric material is a metallic oxide having a perovskiteor ilmenite crystal structure and a dielectric constant of approximately20 or higher.
 54. The capacitor of claim 38 , wherein the dielectricmaterial is selected from the group consisting of BST, PZT, SBT, PLZT,PST, BBT, BT, ST and tantalum oxide.
 55. A memory cell, comprising: asubstrate; a transistor including a gate on said substrate and asource/drain region in said substrate disposed adjacent to said gate; acapacitor comprising an electrode having a platinum-rhodium layer and aplatinum layer on top of the platinum-rhodium layer, wherein theelectrode has a lateral surface aligned with the source/drain region;and a conductive plug providing electrical contact between thesource/drain region and the lateral surface of the electrode.
 56. Thememory cell of claim 55 , wherein the platinum-rhodium layer comprisesan alloy of approximately 3 to approximately 40 percent rhodium andapproximately 60 to approximately 97 percent platinum.
 57. The memorycell of claim 55 , wherein the platinum-rhodium layer has a thicknesswithin the range of about 150 to about 300 Angstroms.
 58. The memorycell of claim 55 , wherein the platinum layer has a thickness within therange of about 50 to about 150 Angstroms.
 59. The memory cell of claim55 , wherein the electrode further comprises a titanium layer beneaththe platinum-rhodium layer.
 60. The memory cell of claim 59 , whereinthe titanium layer has a thickness within the range of about 60 to about100 Angstroms.
 61. The memory cell of claim 59 , wherein the electrodefurther comprises a titanium nitride layer beneath the titanium layer.62. The memory cell of claim 61 , wherein the titanium nitride layer hasa thickness within the range of about 100 to about 150 Angstroms.
 63. Anintegrated circuit, comprising: an electrical circuit containing aferroelectric or high dielectric constant capacitor, wherein thecapacitor has a lower electrode having a platinum-rhodium layer and aplatinum layer on top of the platinum-rhodium layer.
 64. The circuit ofclaim 63 , wherein the platinum-rhodium layer comprises an alloy ofapproximately 3 to approximately 40 percent rhodium and approximately 60to approximately 97 percent platinum.
 65. The circuit of claim 63 ,wherein the platinum-rhodium layer has a thickness within the range ofabout 150 to about 300 Angstroms.
 66. The circuit of claim 63 , whereinthe platinum layer has a thickness within the range of about 50 to about150 Angstroms.
 67. The circuit of claim 63 , wherein the lower electrodefurther comprises a titanium layer beneath the platinum-rhodium layer.68. The circuit of claim 67 , wherein the titanium layer has a thicknesswithin the range of about 60 to about 100 Angstroms.
 69. The circuit ofclaim 67 , wherein the lower electrode further comprises a titaniumnitride layer beneath the titanium layer.
 70. The circuit of claim 69 ,wherein the titanium nitride layer has a thickness within the range ofabout 100 to about 150 Angstroms.
 71. A computer system, comprising: aprocessor; and a memory circuit connected to the processor, the memorycircuit containing at least one memory cell having a ferroelectric orhigh dielectric constant capacitor, wherein the capacitor has a lowerelectrode having a platinum-rhodium layer and a platinum layer on top ofthe platinum-rhodium layer.
 72. A method of forming a lower electrodefor a capacitor, comprising the steps of: providing a substrate; forminga platinum-rhodium layer on the substrate; and forming a platinum layeron the platinum-rhodium layer.
 73. The method of claim 72 , wherein saidplatinum-rhodium layer forming step comprises chemical vapor deposition.74. The method of claim 72 , wherein said platinum-rhodium layer formingstep comprises physical vapor deposition.
 75. The method of claim 72 ,wherein said platinum-rhodium layer forming step comprises sputtering.76. The method of claim 72 , wherein said platinum-rhodium layer formingstep comprises evaporation.
 77. The method of claim 72 , wherein saidplatinum-rhodium layer comprises approximately 3 to approximately 40percent rhodium.
 78. The method of claim 77 , wherein saidplatinum-rhodium layer comprises approximately 60 to approximately 97percent platinum.
 79. The method of claim 72 , wherein theplatinum-rhodium layer is formed to a thickness of about 100 to about800 Angstroms.
 80. The method of claim 72 , wherein the platinum-rhodiumlayer is formed to a thickness of about 150 to about 300 Angstroms. 81.The method of claim 72 , wherein said platinum layer forming stepcomprises chemical vapor deposition.
 82. The method of claim 72 ,wherein said platinum layer forming step comprises physical vapordeposition.
 83. The method of claim 72 , wherein said platinum layerforming step comprises sputtering.
 84. The method of claim 72 , whereinsaid platinum layer forming step comprises evaporation.
 85. The methodof claim 72 , wherein the platinum layer is formed to a thickness ofabout 50 to about 300 Angstroms.
 86. The method of claim 72 , whereinthe platinum layer is formed to a thickness of about 50 to about 150Angstroms.
 87. The method of claim 72 , further comprising forming atitanium layer on the substrate prior to formation of theplatinum-rhodium layer.
 88. The method of claim 87 , further comprisingforming a titanium nitride layer on the substrate prior to formation ofthe titanium layer.
 89. The method of claim 72 , wherein saidplatinum-rhodium and platinum layer forming steps comprise in-situchemical vapor deposition.
 90. A method of forming a capacitor,comprising the steps of: providing a substrate; forming aplatinum-rhodium layer on the substrate; forming a platinum layer on theplatinum-rhodium layer; forming a dielectric layer of a ferroelectric orhigh dielectric constant dielectric material on the platinum layer; andforming an upper electrode on the dielectric layer.
 91. The method ofclaim 90 , wherein said platinum-rhodium layer forming step compriseschemical vapor deposition.
 92. The method of claim 90 , wherein saidplatinum-rhodium layer comprises approximately 3 to approximately 40percent rhodium.
 93. The method of claim 92 , wherein saidplatinum-rhodium layer comprises approximately 60 to approximately 97percent platinum.
 94. The method of claim 90 , wherein theplatinum-rhodium layer is formed to a thickness of about 150 to about300 Angstroms.
 95. The method of claim 90 , wherein said platinum layerforming step comprises chemical vapor deposition.
 96. The method ofclaim 90 , wherein the platinum layer is formed to a thickness of about50 to about 150 Angstroms.
 97. The method of claim 90 , wherein saidplatinum-rhodium and platinum layer forming steps comprise in-situchemical vapor deposition.
 98. The method of claim 90 , furthercomprising forming a titanium layer on the substrate prior to formationof the platinum-rhodium layer.
 99. The method of claim 98 , furthercomprising forming a titanium nitride layer on the substrate prior toformation of the titanium layer.
 100. The method of claim 90 , whereinsaid dielectric layer forming step comprises spinning.
 101. The methodof claim 90 , wherein said dielectric layer forming step comprisessputtering.
 102. The method of claim 90 , wherein said dielectric layerforming step comprises chemical vapor deposition.
 103. The method ofclaim 90 , wherein said dielectric layer forming step comprises ion beamsputtering.
 104. The method of claim 90 , wherein said dielectric layerforming step comprises laser beam deposition.
 105. The method of claim90 , wherein said dielectric layer forming step comprises molecular beamepitaxy.
 106. The method of claim 90 , wherein said dielectric layerforming step comprises evaporation.
 107. The method of claim 90 ,wherein said dielectric layer forming step comprises a sol-gel process.108. The method of claim 90 , wherein said dielectric layer is formed toa thickness of less than about 5000 Angstroms.
 109. The method of claim90 , wherein said dielectric layer is formed to a thickness of less thanabout 500 Angstroms.
 110. The method of claim 90 , wherein thedielectric material is a metallic oxide having a perovskite or ilmenitecrystal structure and a dielectric constant of approximately 20 orhigher.
 111. The method of claim 90 , wherein the dielectric material isselected from the group consisting of PLZT, PST, BBT, BT, and ST. 112.The method of claim 90 , wherein the dielectric material is BST. 113.The method of claim 90 , wherein the dielectric material is PZT. 114.The method of claim 90 , wherein the dielectric material is SBT. 115.The method of claim 90 , wherein the dielectric material is tantalumpentoxide.
 116. The method of claim 90 , wherein said upper electrodeforming step comprises forming a conductive layer on the dielectriclayer.
 117. The method of claim 116 , wherein the conductive layer is alayer of material selected from the group consisting of titaniumnitride, tungsten nitride, platinum, and polysilicon.
 118. The method ofclaim 90 , wherein said upper electrode forming step comprises forming aplatinum layer on the dielectric layer and forming a platinum-rhodiumlayer on the platinum layer.
 119. A method of forming a capacitor,comprising the steps of: providing a substrate; forming a firstelectrode on the substrate, wherein the first electrode has a titaniumlayer on the substrate, a platinum-rhodium layer on the titanium layer,and a platinum layer on the platinum-rhodium layer; forming a dielectriclayer of a ferroelectric or high dielectric constant dielectric materialon the first electrode; and forming a second electrode on the dielectriclayer.
 120. The method of claim 119 , wherein said first electrodeforming step further comprises forming a titanium nitride layer on thesubstrate prior to formation of the titanium layer.
 121. The method ofclaim 119 , wherein said second electrode forming step comprises forminga conductive layer on the dielectric layer.
 122. The method of claim 119, wherein said second electrode forming step comprises forming aplatinum layer on the dielectric layer and forming a platinum-rhodiumlayer on the platinum layer.
 123. The method of claim 119 , wherein saidfirst electrode forming step comprises in-situ chemical vapordeposition.